`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/22 17:12:38
// Design Name: 
// Module Name: instr_mem
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


// module instr_mem(
//     input logic [31:0] pc_adr,

//     output logic [31:0] pc_read
//     );
    
//     logic [31:0] instr[1023:0]; //1kb

//     initial begin
//         //$readmemh("C:/Users/Tianlin/Desktop/instr_test.txt",instr);
//         //$readmemh("C:/Users/Tianlin/Desktop/instr_test1.txt",instr);
//         $readmemh("C:/Users/Tianlin/Desktop/inst_mem.txt",instr);
//     end

//     assign pc_read = instr[pc_adr[11:2]];

// endmodule
module instr_mem(
    input  logic [31: 0]    pc_adr_i,
    input  logic [31: 0]    pc_read_i,

    output logic            en,
    output logic [ 3: 0]    we,
    output logic [31: 0]    pc_adr_o,
    output logic [31: 0]    pc_read_o,
    output logic [31: 0]    pc_write
    );

    assign we           = 4'b0;
    assign pc_write     = 32'b0;
    assign en           = 1'b1;
    assign pc_adr_o     = pc_adr_i;
    assign pc_read_o    = pc_read_i;


endmodule